Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells. These cells comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy band gap than the memory layer. This memory layer sequence is arranged between a channel region within a semiconductor layer or substrate and a gate electrode, which is provided to control the channel by means of an applied electric voltage. The programming of the cell is performed by the acceleration of charge carriers, especially electrons, in the channel region to generate charge carriers of sufficient kinetic energy to penetrate the confinement layer and to be trapped in the memory layer. Source and drain regions are provided at both ends of the channel region to apply the accelerating electric voltage. The threshold voltage of the transistor structure is sensed when the programmed state of the memory cell is read. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide of the semiconductor material and the memory layer is a nitride of the semiconductor material, usually silicon.
A publication by B. Eitan et al., “NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters, volume 21, pages 543 to 545 (2000), describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride oxide that is especially adapted to be operated with a reading voltage that is reverse to the programming voltage (reverse read). The oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm.
The memory layer can be substituted with another dielectric material, provided the energy band gap is smaller than the energy band gap of the confinement layers. The difference in the energy band gaps should be as great as possible to secure a good charge carrier confinement and thus a good data retention. When using silicon dioxide as confinement layers, the memory layer may be tantalum oxide, cadmium silicate, titanium oxide, zirconium oxide or aluminum oxide. Also intrinsically conducting (non-doped) silicon may be used as the material of the memory layer.
It is possible to use the standard planar NROM cell to store bits at both channel ends by the application of reverse operating voltages. This means that two bits can be programmed in each memory cell. But the two-bit separation gets more and more difficult as the locations for charge storage come into close proximity because of the reduction of the cell dimensions, thus putting constraints to the scalability of the planar NROM cell.
The further miniaturization of semiconductor memory devices comprising charge-trapping cells is limited because of the required minimum effective channel length. To obviate this problem, memory cells that are arranged at sidewalls of trenches have been proposed. The gate electrode is arranged within the trench so that a channel extending along the sidewall and/or the bottom of the trench can be controlled. Source and drain regions are located at the upper surface of the device adjacent to the trenches or both at the upper surface and at a bottom region of the trenches. The trench transistor structure is thus appropriate to reduce the required surface area of the memory cell array considerably.